Hi, thanks peter for your comments.
> > Index: locore.s
> > ===================================================================
> > RCS file: /home/ncvs/src/sys/i386/i386/locore.s,v
> > retrieving revision 1.144
> > diff -u -r1.144 locore.s
> > --- locore.s 2001/07/12 06:32:50 1.144
> > +++ locore.s 2001/08/08 17:49:28
> > @@ -374,6 +374,12 @@
> > movl IdlePTD,%esi
> > movl %esi,PCB_CR3(%eax)
> > + testl $CPUID_PGE, R(cpu_feature)
> > + jz 1f
> > + movl %cr4, %eax
> > + orl $CR4_PGE, %eax
> > + movl %eax, %cr4
> > +1:
> > pushl physfree /* value of first for init386(f
> irst) */
> > call init386 /* wire 386 chip for unix opera
> tion */
> > @@ -718,13 +724,6 @@
> > */
> > create_pagetables:
> > -
> > - testl $CPUID_PGE, R(cpu_feature)
> > - jz 1f
> > - movl %cr4, %eax
> > - orl $CR4_PGE, %eax
> > - movl %eax, %cr4
> > -1:
> > /* Find end of kernel image (rounded up to a page boundary). */
> > movl $R(_end),%esi
> This part is fine.
OK, I'll commit this one first.
> > Also I have another thing to be confirmed. Should we utilize TLB by
> > enabling PGE bit at very later stage? I think it would be more
> > efficient to cache page entries with G flag in multi-user environment,
> > not in kernel bootstrap. If we enable PGE bit in locore.s, TLB could
> > be occupied by entries which is referenced by initialization code
> > (yes, most of them are executed only once).
> > # but I could be wrong...
> The G bit does not "lock" the TLB entries in. All it does is stop
> unnecessary flushes when %cr3 is changed. If entries are not used
> for a short while, they will be recycled when the TLB slot is needed
> for something else soon enough. ie: this should not be a problem.
My point is that users need higher system performance in multi-user
environment rather than in kernel bootstrap. Also PGE bit has effects
in multi-user environment where %cr3 is changed frequently.
I think enabling PGE in early stage of kernel bootstrap won't give us
performance advantages, entries which is used in bootstrap will remain
in the TLB as Intel's document says;
3.7. TRANSLATION LOOKASIDE BUFFERS (TLBS)
When the processor loads a page-directory or page-table entry for a
global page into a TLB, the entry will remain in the TLB indefinitely.
The only way to deterministically invalidate global page entries is to
clear the PGE flag and then invalidate the TLBs or to use the INVLPG
instruction to invalidate individual page-directory or page-table
entries in the TLBs.
According to i386/locore.s, it seems that PTEs for kernel text, data,
bss and symbols have PG_G bit, I worry that it is enough many to fill
TLB slot out...
> Regardless of my doubts above, I do have a problem with the patch...
> It only works for the PPro/p2/p3 and not the p4. Is this intentional?
> All have the CPUID_PGE bit. I think the test for cpu_id & 0x600 is
> bogus and should be removed.
Thanks for pointing it out.
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