On Sun, Oct 03, 2004 at 11:21:14AM -0700, Bruce R. Montague wrote:
> > Actually, all Power and PowerPC chips have this...
> Thanks for pointing that out. I believe the entire
> line of IBM virtual memory hardware that supports
> IBM's form of "inverted page tables" is all directly
> related, if not the same, and descends from the
> never-completed 1970s-era IBM "Future System" (FS)
> project. Or perhaps it was a version redone for the
> System/38 that used lessons learned from the FS? Is
> this right? The AS/400 has successfully used this
> architecture for a long time. Most of the other
Don't know. I'm old enough to have worked on those beasts (started
out on S/32 and S/36 actually), but I didn't really know them
under the hoods.
> seem to have never quite caught on. Is this VM unit
> and the Power/PowerPC's the same? They "cheat" a bit
> with a hash table to keep the cost of the associative
> memory down; perhaps increasing its size is the
> natural evolution of this VM architecture? Are there
> any "true" single-level store OSes running on this
> inverted PT hardware? (That is, where RAM is literally
This is what I have, and indeed they use hashing:
"The RS/6000 uses two types of virtual address. There is a single,
flat, system virtual address space with 52-bit addresses. [...] Each
process uses 32-bit addresses, and the per-process address space maps
into parts of the system address space, [...] The 32-bit process virtual
address is divided into 3 parts--a 4-bit segment ID, a 16-bit page index,
and a 12-bit offset in the page. Thus the address space comprises 16
segments, and each segment is 256 megabytes in size. [[Incidentally,
this is quite a big tradeoff, since it means you only have about 10
segments available, which translates in mmap and shared memory are, ahem,
interesting to use on AIX.]]
The RS/6000 has 16 segment registers, which are loaded with segment
descriptors of the current process. [...]
[...] The segment ID identifies the segment register, which is 32 bits
in size. It contains a 24-bit segment index, which forms the 24 high-order
bits of the system virtual address. This is combined with the 16-bit
virtual page index from the process virtual address to form the virtual
page number in the system address space. This must be further translated
to obtain the physical page number.
[...] it maintains an inverted page table called the <i>page frame
table (PFT)</i>, with one entry for each physical page. The system uses
a hashing technique to transalate virtual addresss [...] A data structure
called the <i>hash anchor table (HAT)</i> contains information used to
convert a system virtual page number to a hash value, which points to a
linked list of PFT entries."
Source: Uresh Vahalia, Unix Internals: The New Frontier (which by
the way I highly recommend regardless of the amount of Unix knowledge).
However, as the book points out, the process is slow, so the chip relies
on two optimizations:
"[...] The RS/6000 maintains two separate TLBs--a 32-entry instruction
TLB and a 128-entry data TLB. [[In case of a TLB miss]] the RS/6000 has
separate data and instructions caches. The data cache is 32 or 64
kilobytes in size, and the instruction cache is 8 or 32 kilobyes [...]
These caches are virtually addressed; therefor, address translation is
not required when there is a cache hit."
Note that all sizes are severely outdated, and given that the reference
Vahalia gives is dated 1994, I suspect they are based on the original
POWER CPU. I know for sure recent POWER4 and high-end PowerPC chips
(such as the one Apple calls G5) have a lot more.
> OS/400 is, but maybe an expert knows for sure? OS/400
> runs on modern AS/400's which use the PowerPC, unless
> I'm mistaken... Sorry to have so many questions and
> no answers, hopefully the coffee will kick in soon.
You are right, AS/400 have been running on POWER or PowerPC for a
while now. One of the main advantages to having a HAL that presents
a virtual architecture to the OS.