Re: Triton chipset with 256k cache caches 32M only?

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From
Rodney W. Grimes <rgrimes@GndRsh.aac.dev.com>
Date
15 May 1996 10:11:02
Subject
Re: Triton chipset with 256k cache caches 32M only?
Message-ID
199605151704.KAA04912@GndRsh.aac.dev.com


[ Hide this part ]
> > >>    No, it uses the parity bits. Only 8 syndrome bits are needed
> > >> for 64bit words.
> > >
> > > Hmm. So does that mean the ECC is limited to single (odd
> > >number of) bit errors?
> >
> > ECC has single bit error correction and 2 bit error detection. Better than
> > parity no matter how you slice it.

Only if you have memory that is failing or you need extreamly reliable
operation (good memory should have a single bit error rate of something
like 1 in 10 years).

>
> I have not tried it on D-P, but Rod says that the Triton-II ECC imposes an
> extra delay in memory accesses, i.e. "don't use it".

The cost is about 10 to 15% in memory bandwidth.

> That should be really easy to see if you go looking for it.

Yep... easy to spot in any bcopy benchmark larger than the cache.

--
Rod Grimes rgrimes@gndrsh.aac.dev.com
Accurate Automation Company Reliable computers for FreeBSD


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