> o I-cache coherency
The culprit could be the code fragment in
if (!strcmp((*result)->f_type, "elf kernel"))
__syncicache((void *) (*result)->f_addr,
If f_addr isn't the start of the text segment i.e. if the initial page
wasn't included, then that is what is blowing up.
> Quick question: On ARM and ia64 you need to sync the
> D-cache before you can make the I-cache coherent. That's
> because the I-cache is made coherent with memory and
> not with the D-cache. How's that on PowerPC?
Same - see powerpc/syncicache.c where the d-cache is flushed before
the invalidating the i-cache.