On Tue, Jul 10, 2001 at 12:42:12PM -0400, firstname.lastname@example.org wrote:
> > Instead, AMD implemented the Intel APIC specification;
> > I'm not sure if they did it by licensing the patent
> > (Intel had a patent on the APIC design), or if it's
> > just been long enough for it to come off patent
> The Athlon uses the Alpha's ev6 spec, not the intel spec.
The APIC covers things like how I/O interrupts are routed. The
thing AMD licensed from DEC (or Compaq) is the ev6 "bus" protocol
for keeping the cache contents coherent between CPUs. That is
basically invisible to even OS software (as long as it works),
other then altering how long memory references take.
The current Intel's have a shared bus, and all memory traffic goes
over it, and some cache coherency traffic as well.
The AMD's/EV6's have a memory bus PER CPU plus a coherency bus.
I think the coherency bus may even be point-to-point between the
CPU and coherency controller, not a all the CPUs with the coherency
controller being responsible for routing messages as needed.
It is clearly a more expensive, more complex system. It also allows
much higher memory bandwidth (if two CPUs are looking at different
chunks of the address space they get their own path to memory). If
the coherency "bus" really is point-to-point the coherency controller
has to have a big chunk of SRAM, but you should be able to get
dramatically more CPUs to access memory quickly.
That may explain why you can buy Alpha systems with 40+ CPUs, and
Intel XENON boxes with no more then eight (or is it four?). It is
also part of why the big Alphas are costly, but only part of it...
Not speaking for much of anyone, maybe not even myself
To Unsubscribe: send mail to majordomo@FreeBSD.org
with "unsubscribe freebsd-questions" in the body of the message